a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device and its manufacture suitable for highly integrated and reliable DRAMs (Dynamic Random Access Memories).
b) Description of the Related Art
It is essential to make a fundamental constituent, a memory cell of DRAM, more and more smaller or finer in order to realize high integration and low cost. A general DRAM cell is constituted of one MOS transistor and one capacitor.
In order to make a memory cell finer, it is therefore substantial that how a large capacitance is obtained from a small cell size.
As a method of procuring a capacitance of a memory cell, a trench type cell and a stack type cell have recently been proposed and adopted as the cell structure of current DRAMs. A trench type cell has a capacitor formed in a trench in the substrate. A stack type cell has a capacitor three-dimensionally stacked over the MOS transistor. More improved cell structures have also been proposed, particularly for stack type cells, such as a fin type cell and a cylinder type cell. A fin type cell has a plurality of storage electrodes disposed generally in parallel with the substrate and upper and lower surfaces of each storage electrode are used as a capacitor. A cylinder type cell has a cylindrical storage electrode disposed generally vertically to the substrate.
By using these cell structures and their manufacture processes, it becomes possible to realize DRAMs of 64 Mbit class.
However, a voltage applied to the capacitor electrode of a trench type capacitor forms a depletion layer near the trench so that the charge accumulating region broadens greatly. If trenches of adjacent capacitors are formed near to each other, leak of stored charges may occur and stored data may be lost. It is therefore necessary to broaden the width of an isolation area between cells, i.e., the width of a field oxide film area. This hinders high integration.
From this reason, stack type capacitors are promising devices which may contribute to high integration and high reliability of DRAMs.
A fine stack type capacitor is reported in “A 0.29-Hμm2 MIM-CROWN Cell and Process Technologies for 1-Gigabit DRAMs”, 1994, pp. 927–929.
A cross sectional view of this memory cell is shown in FIG. 29.
In FIG. 28, reference numeral 100 represents a word line or gate electrode, reference numeral 101 represents a first polysilicon plug, reference numeral 102 represents a bit line, reference numeral 103 represents a second polysilicon plug, reference numeral 104 represents a storage electrode, reference numeral 105 represents a dielectric film, and reference numeral 106 represents an opposing electrode. Highly integrated DRAMs are provided by using cylinder type capacitors.
A height of the storage electrode of a cylinder type capacitor is required to be made greater in order to procure a sufficient capacitance even with a small cell area. Therefore, a height difference or step between a memory cell area and a peripheral circuit area becomes large, which becomes a critical issue. For example, in patterning a metal wiring layer on the memory cell area and peripheral circuit area, a size accuracy is lowered because of an insufficient depth of focus of photolithography to be caused by the step.
Although the step between the memory cell and peripheral circuit areas can be removed by filling the concaved peripheral circuit area with an insulating film, an aspect ratio of a contact hole in the peripheral circuit area becomes large, posing another problem of a difficulty of etching control.
As the distance between wiring patterns becomes short as the device becomes fine, a parasitic capacitance of wiring tends to increase.